Semiconductor Engineering

Low Power Design: RTL Power Analysis

In last month’s blog, we discussed and compared various power techniques. A quick recap of these power techniques is shown in figure 1. Selecting between them is often quite challenging. These ...
Semiconductor Engineering

Low-Power Design Is More Than Just Minimizing Power

Engineers are accustomed to making tradeoffs when designing products — faster and more power-hungry, or slower and lower-power; expensive and durable, or cheap and disposable; and so on. The ongoing ...
Electronic Design

Low-Power Design With Multi-VDD Flows

Nearly all designs at advanced process nodes need some sort of power-saving strategy. As more designs employ advanced low-power techniques, design teams are discovering huge implementation hurdles ...
EDN

Low-power design techniques span RTL-to-GDSII flow

With today's increasingly large and complex digital IC and system-on-chip (SoC) designs, design power closure and circuit power integrity are starting to become one of the main engineering challenges, ...
Electronic Design

Embarking on a New Frontier of Power Density with GaN

What all-electric aircraft and GaN FETs have in common. The differences between LLC+Buck and Boost+LLC-DCX circuits. We’ll kick off this article with a power component recently introduced by Efficient ...
Electrical Construction & Maintenance

Electrical Power Design Considerations for All-Electric Hospitals

Redundancy in power sources, including multiple utility feeds and paralleling generators, is crucial for ensuring continuous operation during outages. Proper load assessment and equipment redundancy ...
EDN

Low power design – A case for RTL power analysis

In the last blog, Low-power Hydra, I discussed how power has become a challenge to many designers, even at advanced process nodes. I also recommended that designers should start looking at the design ...